The present invention relates to a nonvolatile semiconductor memory device (EEPROM) constructed by a plurality of electrically programmable and erasable memory cells and, more particularly, to a semiconductor memory device such as an NAND cell type EEPROM, an AND cell type EEPROM, a DINOR cell type EEPROM, and a NOR cell type EEPROM.
As a kind of a semiconductor memory device, there is an EEPROM (Electrically Erasable Programmable Read-Only Memory). Particularly, an AND cell type EEPROM in which plural memory cells are connected in parallel described in, for example, T. Kobayashi et al, IEEE International Electron Devices Meeting”, 2001, pp. 29-32 is known as an EEPROM realizing high integration. A memory cell in the AND cell type EEPROM has an FETMOS structure in which a floating gate (charge trapping layer) and a control gate are stacked via an insulator film on a semiconductor substrate. Plural memory cells are connected in parallel so as to share sources and drains and are connected as a unit to a data line. Such AND cells are arranged in a matrix, thereby forming a memory cell array. Since the plural memory cells are connected in a lump to the data line, it is unnecessary to mount a contact between the data line and the memory cells for each of the memory cells, so that a highly-integrated memory cell array can be realized.
First, the configuration of a memory array in the AND cell type EEPROM will be described in detail. FIG. 2 is a diagram showing the configuration of a block in a memory cell array and a word decoder in the AND cell type EEPROM. An area MB indicated by broken line in FIG. 2 shows an AND cell group called a memory block sharing the same word line and a gate signal of a select transistor. A local drain line LBD in each memory block is connected to a data line extending in plural memory blocks via a select transistor STRD. A local source line LBS in each memory block is connected to a common source line CS via the select transistor STRS. To each of the blocks, a gate signal STD of the select transistor connected to the data line, a gate signal STS of the select transistor connected to the common source line, and memory cell word line signals WL0 to WLm are connected. By the gate signals STD and STS supplied according to a row address and a word line voltage supplied from the word decoder in accordance with the row address, the memory block MB and a row of the AND cell are selected. The word decoder is constructed in an inverter type in which a word driver is mounted for each word line and, for example, a PMOS and an NMOS are connected in series. A power supply VP on the high voltage side is connected to the source of the PMOS side of the word driver, and a power supply VN on the low voltage side is connected to the source on the NMOS side. As input signals of the word driver, word line selection signals SG0 to SGm are connected.
The operation of such an AND cell type EEPROM is performed as follows. Date is written by applying a positive high voltage, for example, 18V to a word line of a selected memory cell and applying a voltage of 0V or about 5V to a data line in accordance with data to be written. When 0V is applied to the data line, the potential reaches the channel of the memory cell via the select transistor STRD and the local drain line LBD. Electrons are injected from the channel to a floating gate of the selected memory cell by Fowler-Nordheim tunneling current. This state corresponds to “0”. On the other hand, when 5V is applied to the data line, the potential similarly reaches the channel of the selected memory cell and acts to reduce the electric field between a control gate and the channel. As a result, electrons are not injected into the floating gate of the selected memory cell. This state corresponds to “1”.
Data is erased on the word line unit basis by applying a negative high voltage to the word line of the selected memory cell. In this case, electrons are ejected from the floating gate toward the substrate by Fowler-Nordheim tunneling current. As a result, the threshold voltage of the selected memory cell shifts to the negative direction and the state corresponding to “1” is obtained.
Data is read by using a phenomenon that current flowing between the source and the drain changes according to the state of the threshold voltage of a memory cell. When the word line of a selected memory cell is set to a read level and current flows, an erase state of “1” is determined. When no current flows, “0” is determined.
In such a memory cell array, plural word lines are arranged at regular intervals in each of the memory blocks, so that the word lines are regularly arranged with regular line widths and spaces in the center of the memory block. On the other hand, in a portion around the border of memory blocks, for example, in an area upper than a word line WL0 or lower than a word line Wm, regularity of wiring arrangement is disturbed. It causes a problem such that patterning of the word lines of, for example, WL0 or WLm at both ends of a memory block is unstable, that is, patterning precision is lower as compared with that of word lines of, for example, WL1 to WLm-1 in the center of the memory block, in which regularity of the wiring arrangement is maintained. Such disturbance of regular intervals becomes more conspicuous as reduction of the memory cell size progresses. For example, as photolithography technique realizing microfabrication of 0.1 μm process or finer, phase shift lithography, particularly, Levenson phase shift lithography is known. In the Levenson phase shift lithography, phases of neighboring patterns have to be inverted. To realize high resolution, it is important to improve the regularity. At the same time, it is indispensable that phases of a light source as an illumination system are aligned. In the case of using a light source having aligned phases, if the regular intervals of the patterns are disturbed, the width of, particularly, the second word line from the end of the memory block tends to decrease due to a change in a development area in the border between rough and fine word line patterns and an optical factor. Although the dimensions can be set to the same from the viewpoint of light intensities, due to variations in the degree of sharpness, that is, contrast of a profile of light intensity, development progress speed varies. When a narrow wordline is formed for the above reasons, coupling between a control gate and a floating gate varies, and there is the possibility that the memory cell characteristics such as write and erase characteristics may be largely varied. Further, when a word line having a very small width is formed, there is the possibility that the word line falls and is short-circuited with a neighboring word line or the gate line of a select transistor, and a defect occurs. Such a problem may similarly occurs in the memories disclosed in JP-A No. 2001-156275 and Y. Sasago et al, “IEEE International Electron Devices Meeting”, 2003, pp. 952-955.
Further, such a problem may similarly occur not only in an AND cell type EEPROM but also in an NAND cell type EEPROM disclosed by, for example, F. Arai et al, “IEEE International Electron Devices Meeting”, 2000, pp. 775-778. FIG. 3 is a diagram showing the configuration of a block in a memory cell array and a word decoder in the NAND cell type EEPROM. An area MB indicated by broken line in FIG. 3 shows an NAND cell group called a memory block sharing the same word line and a gate signal of a select transistor. A local bit line LB in each memory block is connected to a data line extending in plural memory blocks via a select transistor STRD. A local bit line LB in each memory block is connected to a common source line CS via the select transistor STRS.
One memory cell in the NAND cell type EEPROM is similar to that in the AND cell type EEPROM with respect to the point that it has an FETMOS structure in which a floating gate (charge trapping layer) and a control gate are stacked on a semiconductor substrate via an insulator film. Different from the AND cell type EEPROM in which plural memory cells are connected in parallel so as to share sources and drains, the NAND cell type EEPROM is characterized in that plural memory cells are connected in series. Such AND cells are arranged in a matrix, thereby constructing a memory cell array. Since the plural memory cells connected in series are connected in a lump to a data line as described above, it is unnecessary to dispose a contact between the data line and a memory cell for each of the memory cells, and the high-integrated memory cell array can be realized. To each of the blocks, a gate signal STD of a select transistor connected to the data line, a gate signal STS of the select transistor connected to a common source line, and memory cell word line signals WL0 to WLm are connected. By the gate signals STD and STS supplied according to a row address and a word line voltage supplied from the word decoder in accordance with the row address, the memory block MB and a row of the AND cell are selected.
In such a memory cell array of the NAND cell type EEPROM, plural word lines are arranged at regular intervals in each of the memory blocks, so that the word lines are regularly arranged with regular line widths and spaces in the center of the memory block. On the other hand, in a portion around the border of memory blocks, for example, in an area upper than a word line WL0 or lower than a word line Wm, regularity of wiring arrangement is disturbed. It causes a problem such that patterning of the word lines of, for example, WL0 and WLm at both ends of a memory block is unstable, that is, patterning precision is lower as compared with that of word lines of, for example, WL1 to WLm-1 in the center of the memory block, in which regularity of the wiring arrangement is maintained. The NAND cell type EEPROM has the same problem as that of the AND cell EEPROM with respect to the point that the disturbance of regular intervals becomes more conspicuous as reduction of the memory cell size progresses. Therefore, like the AND cell type EEPROM, the NAND cell type EEPROM has a problem of reduction in the word line width and falling of the word line in an end of each memory block.
In a conventional semiconductor memory device such as an AND cell type EEPROM, the programming precision of a word line disposed close to a gate signal of a select transistor in a memory block is lower than that of the other word lines, and there is the possibility that the word line is formed narrower than designed. In this case, characteristics of writing, erasing, and the like of memory cells are largely different from those of memory cells of other word lines, and an operation error may occur. When the line width is decreased severely, there is the possibility that a word line falls and is short-circuited with a neighboring word line or a gate signal of a select transistor, thereby causing a defect.
The present invention has been achieved in view of the circumstances and an object of the invention is to provide a reliable semiconductor memory device capable of preventing a defect which occurs due to reduction in the word line width and falling of a word line caused by disturbance in regularity of the intervals of word line patterns near a select transistor in a memory block.